EE-166: Design of CMOS Digital Integrated Circuits

Course Description:

Analysis and design of MOS based combinational and sequential digital integrated circuits. Industry standard CAD tools (Cadence) will be used extensively in homework and a group final project.

Here is the Green Sheet

Class #	Date	Class Meets	Topic/Notes
1	8/24/2009	Yes	Introduction
2	8/26/2009	Yes	MOS Transistor
3	8/31/2009	Yes	MOS Transistor
4	9/2/2009	Yes	LAB DAY
5	9/7/2009	Yes	MOS Transistor/ Spice
6	9/9/2009	Yes	CMOS Inverter
7	9/14/2009	Yes	CMOS Inverter
8	9/16/2009	Yes	Delay in a CMOS Inverter I
9	9/21/2009	Yes	Delay in a CMOS Inverter II Extra Notes on measuring Delay
10	9/23/2009	Yes	Exam #2 Review
11	9/28/2009	Yes	Exam #2
12	9/30/2009	Yes	Exam Results/Project Management
13	10/5/2009	Yes	Processing/Stick/Switch
14	10/7/2009	Yes	Layout I
15	10/12/2009	Yes	NAND/NOR
16	10/14/2009	Yes	NAND/NOR
	10/19/2009	No (F)
18	10/21/2009	Yes	XOR/AOI
19	10/26/2009	Yes	XOR/AOI
20	10/28/2009	Yes	Review
21	11/2/2009	Yes	Exam # 3
22	11/4/2009	Yes	Latches
23	11/9/2009	Yes	Flip Flops
	11/11/2009	No (H)
24	11/16/2009	Yes	Clocking, Setup/Hold/ Skew, Clock Architectures
25	11/18/2009	Yes	Schmitt Triggers/ Super Buffer
26	11/23/2009	Yes	Power Grid Layout
27	11/25/2009	Yes	LAB DAY
28	11/30/2009	Yes
29	12/2/2009	Yes
30	12/7/2009	Yes

	Sample Final
C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\MT2_F04S.pdf Sample Exam #2	C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\MT2_S05S.pdf Sample Final
C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\finalF03.pdf Sample Exam # 3	C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\finalS03S.pdf Sample Final
Sample Final	Sample Final
Sample Final	Sample Final
Sample Final	Sample Final
Sample Final

Here is the Cadence tutorial.

Here is a case study of and IC project that could be sent to MOSIS. It has all verification steps plus sample ncverilog code.

Here is a case Study of a Ripple Adder.

Kogge Stone Adder Tree verification example

Here is some more documentation on Cadence tools.

Here are the previous design projects.

Here is the course Cheat sheet.

Here is an excel workbook that has the delay calculations for an inverter.

Here is the template for the final oral report in power point.

Sample Report

Here is a quick tutorial on FTP (Moving files from UNIX to home.)

Table 1: Homework

HW#	HW Solutions
HW1	C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\HW1_S06S.pdf C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\HW1S.pdf HWS1
HW2	HWS2
HW3	C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\HW3S.pdf NA
HW4	C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\HW4S.pdf HW4S C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\HW4_S06S.pdf
HW5	HW5S
HW6	C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\HW6S.pdf NA
HW7	C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\HW7S.pdf HW7S
HW8	C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\HW8S.pdf HW8S
HW9	C:\Documents and Settings\Prof. David Parent\Desktop\desktop_2\public_html\ee166\HW9S.pdf HW9S
HW10	HW10S

You can find more Cadence related information at the SJSU IC design group’s Homepage.

Grades as of 15 MAY 2008