EE-166: Design of CMOS Digital Integrated Circuits

Course Description:

Analysis and design of MOS based combinational and sequential digital integrated circuits. Industry standard CAD tools (Cadence) will be used extensively in homework and a group final project.

Here is the Green Sheet

Class 1	Introduction to the course, Teaching Philosophy, Academic Honesty, Design Flows, EDA, full custom design, in class exercises, scaling. Moore’s Law
Class 2	Diagnostic exam based on device physics and digital electronics.
Class 3	Exam Results, Mosfets, scaling, capacitances
Class 4	Get your Unix account ahead of time here! (You need to be behind the College Firewall for this site to work.) You must have paid your fees and be enrolled. You must be enrolled for a day before you try to get your account or it will not work.
Class 5	Spice, Design Flow Capacitance
Class 6	Introduction to the CMOS inverter, switching threshold, noise immunity
Class 7	Continuation of VINTH, variation of noise immunity with VDD
Class 8/9 Extra Notes on measuring Delay	Transient Response of the inverter, Ring Oscillators, Design of inverter for load and propagation delay
Class 13	Stick Diagrams, Processing, Switch logic
Class 14	Layout Cell Based Design Electro migration, Vias
Class 16/17	Introduction to the design of complex CMOS logic gates (NAND/NOR) gates
Class 18/19	AOI, Euler Path
Review
Exam 3
Class 22	Latches
Class 23	Muxed Based DFF Example, Setup, hold, CK-Q
Class 24	Setup Hold CK-Q, skew, wire capacitance, adder example for c interconnect
Class 25	Super Buffer example
Class 26	Power lines, and reducing voltage drops due to di/dt L

Sample Exam #1 Solution	Sample Final
Sample Exam #2	Sample Final
Sample Exam # 3	Sample Final
Sample Final	Sample Final
Sample Final	Sample Final
Sample Final	Sample Final
Sample Final

Here is the Cadence tutorial.

Here is a case study of and IC project that could be sent to MOSIS. It has all verification steps plus sample ncverilog code.

Here is a case Study of a Ripple Adder.

Kogge Stone Adder Tree verification example

Here is some more documentation on Cadence tools.

Here are the previous design projects.

Here is the course Cheat sheet.

Here is an excel workbook that has the delay calculations for an inverter.

Here is the template for the final oral report in power point.

Here is the rubric that will be used to grade your oral report (20% presentation, 80% proving it works)

Here is a quick tutorial on FTP (Moving files from UNIX to home.)

Table 1: Homework

HW#	HW Solutions
HW1	HW1S
HW2	NA
HW3	HW3S
HW4	HW4S
HW5	NA
HW6	HW6S
HW7	HW7S
HW8	HW8S
HW9	HW9S

You can find more Cadence related information at the SJSU IC design group’s Homepage.

Grades as of 15 MAY 2008