Check to see if you are correct working directory. Double click on the terminal icon in your common desktop environment and a command window will appear (Figure 1). Type in pwd which stands for “print working directory”, this command will show you if you are in the correct working directory.

Figure 1: Terminal

Terminal in view symbol is not found in view schematic

Figure 2: CIW messages when checking and saving schematics.

Often times when adding pins to the schematic capture students forget to change the direction of the pin from input to output (or they have missed entered a pin (terminal) name. Check the “Add pin” window to see if the pin being added is in the correct direction. (See Figure 3 below).

Figure 3: Add pin pop-up Change this to input, output or input/output as needed

My output waveforms hardly change!

There could be various reasons for this problem. A few common ones are listed below.

If your outputs look like Figure 4 below, check your test bench to see if the unit for the capacitor in your circuit is correct. The units should be in “femto” farads, so make sure to type in a lowercase “f” as shown’ in Figure 5 below.

Figure 4: Output Simulation

Figure 5: Add instance pop-up

This value could also be in pico-farads “pF’

If your outputs are changing but the voltage levels are really small in value (see Figure 6) check to see that you are using V_ddand not V_ccyour schematic capture or your test bench.

Figure 6: Output Simulation

If your output simulations are showing fluctuations but the voltage level is always high (as in Figure 7) go to your schematic capture and check to see if the body of the pmos is tied to Vdd and the body of the nmos is tied to ground as shown in Figure 9.

Figure 7: Output Simulation

Figure 8: Schematic capture of a two-input nand gate Body of pmos should not be connected to the drain

Figure 9: Corrected Schematic of two-input nand gate

My DC response is zero.

Figure 10: DC response

The DC response is zero because you are selecting the wrong voltage source in the “Select Component” option (see Figure 10 below).

Figure 11: Setting up DC analysis

Do not choose the V_dc source as that is the biasing of the circuit. Choose the source which is the input to the circuit that you are testing. An example of a nand test bench is given below in Figure 11.

Figure 12: Setting up a correct testbench This is the input to the circuit and should be chosen for DC analysis

My layout doesn’t display all the layers.

Figure 13: Layout view - all layers are not showing up

This happens because you have not set up the display levels correctly in the display options window. To set up the display so that all will appear goto Options—Display and fill up the pop-up as shown in Figure 13 below.

Figure 14: Setting display options Display level should be set form 0 to 20 so that all layers are visible

How do I know that my layout is working?

First make sure that you are running your test bench from extracted view and not from schematic. Your simulation curves from layout should look almost the same as that from schematic. The curves would just be “shifted” a little because you extracted parasitic capacitances. Too run test bench from extracted view, goto the Affirma Analog pop-up, goto Setup…Environment Options. A pop-up like Figure 14 will appear. Type in extracted in front of specterS and click on apply. Now your simulations will run from extracted. If you want to run simulations from schematic again, go to the same window and delete the word extracted, this will enable you to run your simulations from schematic again.

Figure 15: Setting-up simulation options Type in extracted to run simulation from layout

Layout verses Schematic errors (LVS)

Figure 16: Completion of LVS check

The above pop-up doesn’t necessarily mean that your LVS check is correct. To determine if your LVS is really successful you have to check the output log. In the LVS pop-up (Figure16 below) click on output, this should display a log giving you details of your LVS check.

Figure 17: Layout verses schematic pop-up Click on output to display log

A correct LVS log should give you zero unmatched instances, zero unmatched nets and zero unmatched terminals. See Figure 17 for more details.

Figure 18: LVS log

Other common errors that come up on the LVS log are not having the correct I/O type or the correct pin type. In addition, when you type in terminal names everything has to be in lower case. See example below. This should be set accordingly

Figure 19: Setting up pins for layout

Should be set to ‘metal 1’ Everything should be in lowercase characters

My files cannot open for edit, query asks me to open it for read-only.

Figure 20: Open for read only pop-up

This happens because two people are using the same account and are trying to open the same file at the same time. If both of you want to work on the same circuitry at the same time one of you has to make a copy of that file.

To do this right click on the cell view that you want to work on and select the copy command. A pop-up like Figure 20 should appear.

Figure 21: Pop-up showing how to copy files

In the above example the cell nand is in the library called “ERROR”. To make a copy of this nand, type in a new name in the area called “Cell” under the “TO” heading and click OK. This should make an exact copy of your cell but will have a different name. This way two people can work on it at the same time because it is under different names.

Unsuccessful Simulation

Figure 22: CIW showing unsuccessful simulations

There could be many reasons for this error but the most common one made by students is that they don’t change the simulator to specterS. Check to see if your simulator is set to specterS. In the Affirma Analog pop-up goto Setup…Simulator/Directory/Host, a pop-up like Figure 22 should appear.

Figure 23: Setting up simulator Make sure this is set to spectreS and not hspice

Figure 21 directs you to the output log. If you want to know why your simulation failed you could check the output log. (note this output log is different than the one in the LVS window). To check output log: in the Affirma Analog window goto Simulation……Output log this should bring up a pop-up like below. (Note: This output log corresponds to Figure 21)

Figure 24: Output log displaying errors

How do I show all possible states in my simulation?

The figure below shows the simulation of a two-input nand gate but all the states are not shown and so you cannot be sure if your simulation is correct.

Figure 25: Two-input nand simulation showing state 00 and 11

To display state 01or 10 change the pulse width and period of the second voltage source so that it is double the first voltage source.

Figure 26: Setting up properties for first voltage source

Figure 27: Setting up properties for second voltage source

Notice that the pulse width and period is double the previous figure

This will now give you an output displaying all states, which is shown in the figure below.

Figure 28: Two input nand simulation showing all states

FAQ

Other Resources for Information:

This is a really good HSPICE Tutorial:

http://www.ee.washington.edu/class/cadta/hspice/

This is a SpecterS tutorial using the 741 as an example: http://www.d.umn.edu/~bshaer/cadence/ece3235/spectre.html

This tutorial is on Affirma Analog:

http://www.egr.msu.edu/classes/ece813/mason/tutorial-c.htm

This one is a basic tutorial on the complete digital design F-B design flow: http://vlsi.wpi.edu/cds/

Here is another (good) full tutorial:

http://www.ee.vt.edu/~ha/cadtools/cadence/gate.html

This one is Edgar Sanchez’s website. It has nothing to do with cadence but it’s the best analog design website there is out there. Check it out when you have some time:

http://ee.tamu.edu/HOME00/00_PEOPLE/bios/bsanchez.html