David
W. Parent
One Washington
Square
EE Department
San Jose State
University
San Jose CA, 95192-0084
Fall Spring Office Hours:
ENGR 355
M:
10:15-12:15
T:
10:00-12:00
W:
10:15-11:30
W: 2:00-4:00
F: After EE198A lets out
Summer/Winter:
Email Only
Please
make an online appointment for office hours here.
Voice 408-924-3963
(Email is better.)
FAX 408-924-3925
E-mail: david.parent@sjsu.edu
Web: www.engr.sjsu.edu/dparent
Class web pages
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Solid State Physics |
Intro to IC processing |
Design Fabrication and test of CMOS circuits |
EE-166 Design of CMOS Digital Integrated Circuits |
High Speed CMOS Circuits |
Principles of Device Physics |
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Analog IC Transistor Process Design |
Chemical and Materials
Engineering & Electrical Engineering |
Critical Path for Electrical Engineers |
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IC Group
Design Resources and Cadence
Tutorials
Cadence Help Cadence Tutorials Friday Lab Meetings Athena/Atlas
Resources
Help for EE167, EE221, EE222 students doing process simulation Need A UNIX Account (Cadence/Synopsys)? You need to be a registered student and have paid your fees for the semester. It takes 24 hours after registering and paying your fees for your account to be active. You need to be behind the College’s fire wall for this to work. Use the pc’s in room 387. Cadence University Member Website
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