The ALU is an essential part to the construction of a single-cycle processor. It performs all the necessary operations that are required to implement the single-cycle machine. More specifically, the ALU has the tasks of addition, subtraction, multiplication, division, logical operation, shift, and comparison of the operands of interest. The essentials to a successful ALU are the efficient usage of control signals and the correct manipulation of the provided data. In addition, the ALU can be separated into several main sections that performs the required tasks. Justifiably, these sections are the addition, subtraction, and comparison; the shift; the logical operations; and finally the multiplication and division. A divide and conquer approach simplifies the design and ease of debugging by dividing the ALU into different sections, testing individual sections and combining them by the corresponding higher level modules. The full ALU design is coded by Verilog HDL, syntax checked by Verilint tool, simulated through Cadence® Verilog-XL® tool, visual checked all the signals input and output by Signal Scan ® tool. The reason of using those state-of-the-art tools is because they are one of the popular tools in the industry currently.

Each of the modules has its own set of I/O's and control signals. The descriptions of the signal and control lines are as follows.

ALU_top.v:

The ALU_top is the top level of the design. It has an ALUcontrol input that selects between the various modules, including the Func, Shifter_32, And_or Mult_divide. Each of these modules contains the logic to perform the corresponding operation. The ALU is also responsible for outputting the final result, as well as the status after the execution of the operation. The ALUcontrol is a 7-bit input control signal that determines which operation to execute as a result from the opcode decoding. The input Clk signal is for synchronous operation. Inputs, A and B, are each 32-bit in size and are the main operands for the various operations. The input control signal, Reset, is mainly used for the Mult_divide module to return to the first state of the operation since the multiply and divide logic is based on state machines. Similarly, the input control signal, Start, is also used for the Mult_divide module to begin the execution. There are also four outputs on the ALU_top. The output signal, Done, indicates the completion of the requested operation. The 4-bit output Status signal acts as a status flag. More specifically, there is the Negative flag, that is set for negative results, the Zero flag, that is set when the output is a zero, the Overflow flag, that is set when there is an overflow in the calculation, and the Carry-out flag, that is set when there is a carry-out from the result. Outputs, Y and Z, are each 32-bit that are used to output the final results from the ALU execution.

The ALU_Control Module provides the ALU_top.v the correct ALUcontrol signals in terms of which operations need to be performed. It generates these signals from interpreting the opcode and function_field inputs. The input Clk signal is for synchronous operation. The 6-bit input, Opcode, provides the operation and format of the incoming instruction. The 6-bit input, Function_field, selects the specific variant of the operation. The 7-bit output, ALUcontrol determines which operation is to be executed and the corresponding module to perform this task.

Func Module:

The Func Module performs the add, subtract, and slt operations. The Func Module also calls out the Adder_CLA for addition based operations. The 2-bit Funct input selects specifically which operation is executed. Inputs, A and B, are each 32-bit data that are to be operated upon. The input Clk signal is for synchronous operation. The Ena input signal is to enable the operation. The Signed_op input indicates if the operation is to be performed on signed or unsigned data. The 4-bit output Status signal acts as a status flag as a result from the operation. Signal, Y, is a 32-bit resultant output.

Adder_CLA Module:

The CLA Module performs the add/sub operation by the carry-look ahead method. The Cin input is the carry-in bit. Inputs, Operands1 and Operands2, are each 32-bit operands that are to be operated upon. The Cout output is the carry-out bit resulting form the operation. Signal, Y, is a 32-bit resultant output.

Shifter_32 Module:

The Shifter_32 Module performs the arithmetic and logical shifts operations. In order to accomplish this task, it needs control signals that specify which type of shift operation to perform. The input Clk signal is for synchronous operation. The Ena input signal is to enable the operation. The input In signal is for the data to be shifted. The 4-bit input, Shift_amount, provides the amount for the data to be shift by. The control input signal, Right, indicates the direction to shift the data. The control input signal, Arithmetic indicates if the shift type is to be arithmetic or logical. Signal, Y, is a 32-bit resultant output.

AndOr Module:

The And Module has the responsibility to perform the logical operations, mainly logical And and logical Or. To support this task, there is an input control signal, And_or, to distinguish between the two logical operations. The input Clk signal is again for synchronous operation and the Ena input signal si to enable the operation. Inputs, A and B, are each 32-bit in length. The output is through the 32-bit Y data line.

Mult_divide Module:

The Mult_divide Module incorporates both the multiplication and division operation. In order to accomplish this task, it needs to call out for a 65-bit shifter module, Shifter_64, which is similar to the 32-bit shifter except the former could support a greater range of data. In addition, this module also calls out the Func module to perform the addition and subtraction operations that are incorporated in the multiplication and division operations. The multiplication technique is based on Booth' Algorithm. The division technique is based on the 3rd version of division by Patterson and Hennessy. The input Clk signal is for synchronous operation. The Ena input signal is to enable the operation. Inputs, A and B, are each 32-bit data that are to be operated upon. The input control signal, Reset, is used for the Mult_div module to return to the first state of the operation. Similarly, the input control signal, Start, is also used for the Mult_div module to begin the execution. The control signal input, Mult_div, determines if the operation is specifically for multiplication or division. The control signal input, Signedop, determines if the operands are for signed or unsigned operands. Output, Y, is a 65-bit data that acts as the resulting output. The output signal, Done, indicates the completion of the requested operation. The 4-bit output Status signal acts as a status flag.

Each member had a fair share of the work. We basically followed the project task distribution that we generated in the preliminary report. However with two of the members being lees familiar in the verilog code than the third, Van had to spend more time decoding and debugging our work. Howard worked on the design and coding of the logical operation. Mike concentrated on the design and coding of the shift operations. Van worked on the addition and subtraction operations. Together, we attempted the multiplication and division design. The consensus among the group is that an equal grade should be given to each of the members. We felt that we all contributed to the project to the best of our ability and should be graded on the same level.

Many of our design logic are adopted from the ideas of Patterson and Hennessy. We used their concepts and implemented our design in a similar fashion. Overall, the design of the ALU was rather successful. We met the design specifications to perform the various operations; including the add, subtract, shift, compare, and logical operations. Each of these operations was achieved in our design. The only drawback was during the design of the multiplication and division operations. We had complications in terms of combining the two operations. We wanted to combine them to operate more efficiently. The problem, however, was due to the resultant being different in size for the two operations. More specifically, the multiplication operation requires a 65-bit output due to overflow while the division operation results in the 64-bit output. In addition, the simulation of this operation was rather time-consuming. There were a lot of intermediate shifts and math operations that supported this operation. As a result, the total operation involved a tremendous amount of time and patience.

The group had no main pleasures or dislikes to this project. If anything, the time for simulation of the multiplication operation was not very desirable. However, all the achievements in terms of the other operations balanced the trial and error process of the multiplication operation. The process of learning the new code, for the two members, whom has little exposure to the syntax, was also rather challenging. Fortunately, there was one member who shared her expertise and knowledge with the other members.

This first project was an attempt to familiarize us with the ALU and its design steps. This experience and knowledge will be expanded in the design of the rest of the single cycle processor. In fact, the ALU of this project can be implemented into the single cycle machine. This single cycle machine will include the register files, instruction decoder, data memory, control signals, and the ALU. As a group, we are excited about the challenge of the second phase of the project. The first project gives us a good indication of the work involved in completing the rest of the project. Clearly, a good approach to the design will be crucial to the rest of the main project.

Shifter64 Module

ALU Controller

ALU Controller Test

alu.f (to compile with VerilogXL)