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EE271    Advanced Digital System Design and Synthesis         Fall 2009

 

I will NOT respond to questions regarding UNIX (or LINUX) such as commands in .cshrc, login files, etc. Students must have basic knowledge about UNIX (or LINUX) before taking this class. Additional related information is at the bottom of this page and in the tutorials

 

-        Course syllabus (all students must read and follow the class policies stated in the course syllabus)

-        Class meeting: Monday & Wednesday, 18:00 – 19:15, Clark 310

-        You can download a student version of SILOS here

-        You can download free student version of ModelSim PE here

-        Verilog HDL Quick Reference Card by Qualis Design Corporation

 

All questions regarding EDA tools and laboratory, please come to my Teaching Assistant’s office hours.

 

Teaching Assistant:

Mr. Akash Patel

Lab/office hour:          Friday 17:00 – 18:00, E289/E291 (Cadence Lab)

Email:                         akash_0406@yahoo.co.in

 

Next Lecture:

Continue Chapter 5

 

Lecture Notes

Note that lecture notes will be deleted when discussion started in class

Chapter 6

Chapter 7

 

Homework/Mini Project Assignments

HW#6 (due Wednesday 11/04/2009) solution

HW#7 (due Wednesday 11/18/2009)

HW#8 (due Monday 11/30/2009)

HW#9 (due Monday 12/07/2009)

 

Exam Schedule and Policies

          Final exam: Monday December 14, 2009, 17:15 - 19:30

 

Final Project

          Final Project Assignment

          Final Project Report Template

          Final project report due: Thursday December 17, 2009, before 11:00AM

 

Tutorials

-    VCS Tutorial

-    Silos Tutorial

-    Design Analyzer Tutorial

Temporary solution for design analyzer software:

1.  Executing the design analyzer by command

     "/apps/design_analyzer.csh" instead of " design_analyzer &"

     as shown in the tutorial

2.  These are my .cshrc, .login, and .synopsys_dc.setup files

     If VCS and/or design_analyzer do not work on your account,

     please create your .cshrc, .login, and .synopsys_dc.setup files

     from mine (make sure to save your old ones)

     make sure you have “setenv VCS_ARCH_OVERRIDE linux”

     statement in your .cshrc file and each “setenv” statement MUST start

     a new line.

3.  If you want to use design_analyzer and/or VCS remotely

     then you must install VNC on your PC. Instructions for

     downloading, installing, and setting up VNC is at

     https://unix.engr.sjsu.edu/wiki/doku.php?id=vncaccess

     and please follow the “VNC Tutorial” closely.

     Currently, design_analyzer does NOT work remotely with SSH

     no matter if you have Hummingbird/Exceed installed on your PC.

 

Notes on Setting up Attributes and Constraints

 

Unix Accounts on Cadence Laboratory

        Rooms E289 and E291 are Cadence laboratories installed with Cadence and Synopsys software tools. Each registered SJSU student should automatically have a Unix account (one account per student, NOT per class) so if you do not know your login name and password, you can find out at https://unix.engr.sjsu.edu/wiki/doku.php

        For Unix tutorial materials and other documents related to Cadence laboratory, please consult Prof. Parent’s website at

      http://www.engr.sjsu.edu/~dparent/ICGROUP/index.htm

      http://www.engr.sjsu.edu/dparent/

        If you have problems with your Unix account, you can try to request for helps at https://unix.engr.sjsu.edu/wiki/doku.php. Note that you must make sure that you set up your account correctly.