EE225A: Analog IC Transistor Process Design

David W. Parent

Associate Professor

EE Department SJSU

PH: 408.924.3963

EM: dparent@email.sjsu.edu

HP: http://www.engr.sjsu.edu/dparent

Course Description:

Advanced process design, fabrication and testing of transistors for analog integrated circuits, design of statistical process control procedures for yield management, industry standard TCAD tools (Synopsys) and IC fabrication equipment will be used extensively in lab.

This is a team-oriented, interdisciplinary course enrolling EE, MatE, ChE, ME, Chemistry and Physics majors. Each student brings a different background to the course. The laboratory is the central theme of the course. This course will require a considerable amount of work outside of regularly scheduled class time so be prepared to invest a lot of time.

Green Sheet/ Syllabus

Pixel Level Intensity to Digital Converter

2 Mask Sentaurus Work Bench File

Simple NMOS MIS Work Bench File

Device Test Manual (MOSFETS, DIODES, ICSMETEIRCS)

Synopsys TCAD Tutorials

Synopsys TCAD Manuals

Synopsys Sdevice, Structure editor SWB Example

Synopsys Sprocess Diode Example

NMOS MIS VT, NMIN SWB Example

2MASK MOS CAP Example to set substrate doping

4Mask 2-D transistor Example

2Mask 2_D transistor Example

1-D diffusion process simulation

Unix Tutorial	Synopsys Sdevice, Structure editor SWB Example	Synopsys Sdevice, Structure editor SWB Example
Synopsys Sprocess Diode Example	(MIS TCAD #1) This SWB workbench file is used to model an MIS 1-D N capacitor. Oxide thickness (TOX in microns) and substrate doping (NA per unit cm) are variables entered into structure editor, and then a CV analysis is done with device with VT, N extracted with inspect. Thisis used to verify the grid spacing and TOX, NA pairs for a specified VT.	(MIS TCAD #2) This SWB workbench file is used to model an MIS 1-D N capacitor. The process recipe for the oxide thickness is modeled in sprocess. GateOX_Time is the growth time in minuests and Gate_Ox_Tmp is the growth temperature in Celsius. Substrate doping (NA per unit cm) is variables entered into sprocess, and then a CV analysis is done with device with VT, N extracted with inspect. This is used to verify the grid spacing and the growth recipe for the gate oxide gives a VT for a given NA.
(MIS TCAD #3) This SWB workbench file is used to model an MIS 1-D N capacitor. The Imp-lant energy/dose along with the well drive time and temperature are set as variables in sprocess. The process recipe for the oxide thickness is modeled in sprocess. This is used to verify the grid spacing and the inplant/does well drive and oxide growth recipe for the gate oxide gives a VT.	(MIS TCAD #4) This SWB workbench file is used to model an MIS 1-D N capacitor that includes all process parameters of the 4-mask nmos process.

Class 1: Introduction	Diffusion	Oxidation	Etching	Photolithography
Statistical Process Control 1	Statistical Process Control 2	Simple Current Mirror Case Study	Class 2: MIS structures, CV, and VT	Safety in the MPEL
4 Mask NMOS Process Documentation	4 Mask testing Guide	2 Mask NMOS Process Documentation	MIS PROCESS TCAD SIO2 Example	Diffusion into Poly Si mini case study.
SPC Western Electric House Rules	Sample Report	4 mask documentation	MIS Case Study	Registration Error Data Spring 2009
Sample Analog Report	Sample Processing Report (The EMBC 2009 paper is probably a better template, this year we used CV mostly for design.)	Gm/id ltspice file

HW1 HW 1 Solution	HW Solution #2	H3 Full MIS design
HW 4 SPC, DATA, Solution	Sam Traveler Janet Traveler Sergio Traveler

Processing Videos:

Photolithography Singe	Photolithography Load Spinner for Adhesion Promoter	Photolithography Spin on Adhesion Promoter	Photolithography Bake Adhesion Promoter	Photolithography Spin on Resist	Photolithography Pre-Bake Resist	Photolithography Expose Resist	Photolithography Develop Resist	Photolithography HardBake Remove Wafer
BOE Etch: place wafers in BOEr	BOE Etch: place wafers in dump rinser
Strip Photo Resist in Piranha 1	Strip Photo Resist in Piranha 2
Spin ON SOG
Load wafers into wafer Carrier	Load Wafers in Furnace	Push Wafers into Furnace
Strip SOG
Gate Clean SC1	Gate Clean SC2
Metal 1 Etch	Metal 1 Resist Strip
Anneal 1	Anneal 2	Anneal 3	Pull Wafers