San José State University (logo)

David W. Parent

EE Department
EE-224 High Speed CMOS Circuits      

 

Course Description:

Analysis and design of high speed CMOS digital integrated circuits; Dynamic circuit techniques; semiconductor memories, adder, multiplier, shifter architectures, Cadence System Tools will be used extensively. Prerequisites: EE166, EE221. 3 units

!! Fall 2005 Grades!!

Textbook:

N. Weste and D. Harris, CMOS VLSI DESIGN, Third Edition, ISBN 0-321-14901-7

(David Harris’s Website : http://odin.ac.hmc.edu/~harris/class/e158/)

 

Cool Digital Arithmetic Website:

http://www.ecs.umass.edu/ece/koren/arith/simulator

 

The other instructor Morris Jones has a website more fully developed than mine.

www.engr.sjsu.edu/mjones

Classes

 

Class
Remark
Design Flow
Review of MOSFETS
CMOS Inverter/Complex AOI Logic/Pass gates/Mux/SubThreshold Operation
Modelling Delay in Static CMOS Circuits
Developing a Delay model
Class7
Area Delay Model
Logical effort
Other Logic Styles
XOR Gates/Design Test benches/Dynamic gates with logic effort.
Test Bench Examples
Sizing Dynamic Gates
Introduction to adders
Introduction to adders - II
Class16
Class17
Class18
Adders and Multipliers
Design of 16bit Adder at 4GHz
Two phase clocking
 

Homeworks

 

HW
Remark
HW4

Resources