This page shows how Cadence tools are used at SJSU to teach IC design, as well as links to tutorials we have developed that teach IC design and the use of Cadence tools. We are currently using the IC6.0, SOC4.1, TSI4.1, LDV5.1, and SPR5.0 Streams.
Links to tutorials that teach IC design and Cadence Tools:
· A tutorial that shows how to verify the logic of static CMOS gates using NCverilog
· A tutorial showing the basics of UNIX need to run Cadence tools
· A FAQ for when student get stuck using Cadence tools
·
Contact Information: Associate Professor David W.
Parent EE Department SJSU Room 355 PH: 408.924.3963 FX: 408.924.3925 Email: dparent@email.sjsu.edu
A tutorial on how to use IIT’s
standard cell Library
· Tutorial on installing the NCSU CDK
Case studies that used Cadence tools:
Pervious Projects can be found at here.
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warranty of any kind. No statement is made and no attempt has been made to
examine the information, either with respect to operability, origin,
authorship, or otherwise. Please use this information at your own risk. We
recommend using it on a copy of your data to be sure you understand what it
does under your conditions. Keep your master intact until you are satisfied
with the use of this information within your environment.”
Class Websites that use Cadence Tools:
· EE224 High Speed CMOS Circuits
Table 1: Estimated Cadence Tool usage by class Spring 2009.
|
Course |
Virtuoso Schematic Capture |
Virtuoso
Symbol |
Spectre |
NC_verliog |
Virtuoso
Layout |
|
COMPE179 |
|
|
|
19 |
|
|
EE179 |
|
|
|
42 |
|
|
COMPE140 |
|
|
|
31 |
|
|
EE166 |
60 |
60 |
60 |
60 |
60 |
|
EE223 |
32 |
32 |
32 |
|
32 |
|
EE224 |
104 |
104 |
104 |
104 |
104 |
|
EE270 |
|
|
|
69 |
|
|
EE271 |
|
|
|
68 |
|
|
EE275 |
|
|
|
71 |
|
|
EE297 |
20 |
20 |
20 |
20 |
20 |
|
EE198A/b |
4 |
4 |
4 |
4 |
4 |
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Site last updated on 19 August 2009.