David W. Parent

One Washington Square

EE Department

San Jose State University

San Jose CA, 95192-0084

Office Hours:

ENGR 355

M:12:45-15:15

T:12:45-15:15

Voice 408-924-3963

FAX 408-924-3925

E-mail: dparent@email.sjsu.edu

Web: www.engr.sjsu.edu/dparent

Biography and Vita

Class web pages

EE-128 Solid State Physics	EE/MatE-129 Intro to IC processing New Lab!	EE/MatE-167 Design Fabrication and test of CMOS circuits	EE-166 Design of CMOS Digital Integrated Circuits	EE-224 High Speed CMOS Circuits	EE-221 Principles of Device Physics Solar Cells	EE Department Brochure IEEE Section Meeting November 5’th 2005
EE198 Senior Design	EE 225A Analog IC Transistor Process Design

IC Group Design Resources and Cadence Tutorials Cadence Help Cadence Tutorials Friday Lab Meetings Athena/Atlas Resources Help for EE167, EE221, EE222 students doing process simulation Need A UNIX Account (Cadence/Synopsys)? You need to be a registered student and have paid your fees for the semester. It takes 24 hours after registering and paying your fees for your account to be active. You need to be behind the College’s fire wall for this to work. Use the pc’s in room 387. Cadence University Member Website Want to be an EE? (PDF)