EE 178 Syllabus

The downloadable version of the syllabus is available here.

Course Title: Digital Design with FPGA

Meeting:
MW 19:30 - 20:45, Engr 336
Lab Open Lab, E 305

Instructor:
Dr. Tri Caohuu, ENG 375
Email: tri.caohuu@sjsu.edu
Tel: (408) 924 3951

Course Outline:

This class covers digital design technologies as they relate to synchronous digital systems using Field Programable Gate Array (FPGA). Students are required to do lab projects using of CAD tools for the design, simulation, and implementation of systems with FPGA's.

Prerequisite: EE118

 


 

 

   
   
   
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  Copyright 2006, Dr. Tri Caohuu, All Rights Reserved.